1. Field of the Invention
The present invention relates to memory systems, and more particularly, to a method and apparatus for addressing and accessing information in cache memories, which may be used in computer systems or other electronic devices.
2. Art Background
It is common in many data processing systems to utilize a high speed buffer memory, referred to as a "cache", coupled to a central processing unit (CPU) to improve the average memory access time for the processor. The use of a cache is based upon the premise that over time, a data processing system will frequently access certain localized areas of memory. The cache typically contains a subset of the complete data set disposed in the main memory, and it can be accessed very quickly by the CPU without the need for accessing main memory. If data and instructions are retrieved from main memory and are placed in cache memory as they are used by a program, and if the system looks first to the cache memory to determine if the information required is available there, then the system will often find the desired information in the cache memory and will, consequently, operate at a higher speed. A performance advantage is realized because statistically, information that has just been used in any particular portion of a process is more likely to be required immediately than is other information which has not been recently used.
The prior art teaches a variety of caching systems. In one type of caching system, both the cache memory devices and the CPU are coupled to a system bus. The CPU issues memory requests over the system bus to the cache memory. There is a "hit" when the requested data and/or instructions are found in the cache memory; in such a case, the information is fetched from the cache and sent over the system bus to the CPU. If the desired information is not found in the cache memory, it must be obtained from the main memory. The procedure for accessing the main memory is well-known in the art and will not be further described herein. Other systems utilize a similar approach wherein the CPU and the cache memory are located on a single semi-conductor device ("chip").
One representative prior art system is illustrated in FIG. 1. As shown, a CPU 10 is coupled to a bus 12 for communication with a plurality of cache memories 14, 16, 18, and 20. Each of the cache memories is coupled to the bus 12 to permit the memories to receive memory operation requests from the CPU 10. A logic control circuit 22 is also coupled to the system bus 12 and to each of the cache memories, as shown in the figure. The logic control circuit 22 is also coupled to an output select multiplexor 24, as are data output lines 26, 28, 30, and 32 from each of the respective cache memories. In operation, the CPU 10 issues a memory request, such as a read or write request, in conjunction with a memory address; this procedure is well-known in the prior art. However, to avoid confusion and ambiguity in the system illustrated in FIG. 1, the logic control circuit 22 must provide a chip select signal ("CS") to the particular cache memory device to which the memory request is directed. Since each of the cache memories, 14, 16, 18, and 20 is coupled to the bus 12, each will sense the memory request and address sent by the CPU. The logic control circuit must sense the memory request and, depending upon the address of the request, enable the appropriate cache memory by issuing a chip select signal to the selected memory device. Thus, the logic control circuit 22 determines which of the cache memories will respond to a particular memory request issued by the CPU 10. The logic control circuit 22 enables the output select multiplexor 24 to couple the output of the responding cache memory to bus 12 for receipt by the CPU 10.
Together, the logic control circuit 22 and the output select multiplexor 24 are generally referred to as "glue logic". Glue logic reduces system performance by adding additional electronic delays in the system and adds to the cost of the memory system by requiring additional semi-conductor components.
As described, the present invention provides an improved cache memory system and a method which overcomes the limitations of the above-described prior art systems. The present invention achieves greater cache memory sizes through the use of cascaded cache memory devices without the performance degradation introduced by external glue logic circuitry previously required by prior art methods.